View SC2621STRT_4124043.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

500kHz Voltage Mode PWM Controller With Linear Power Regulator
POWER MANAGEMENT Description
The SC2621 provides the control and protection features necessary for a synchronous buck converter and a linear regulator in high performance graphic card applications. The SC2621 is designed to directly drive the top and bottom MOSFETs of the buck converter. It uses an internal 8.2V supply as the gate drive voltage for minimum driver power loss and MOSFET switching loss. It allows the converter to operate at 500kHz switching frequency with 4V to 16V power rail and as low as 0.5V output. The SC2621 is capable to drive a N-type MOSFET in a linear regulator with as low as 0.5V output. The SC2621 features soft-start, supply power under voltage lockout, and hiccup mode over current protection. The SC2621 monitors the output current by using the Rdson of the bottom MOSFET in the buck converter that eliminates the need for a current sensing resistor. The SC2621 is offered in a SOIC-14 package.
SC2621
Features
u u u u u u u u u
500kHz switching frequency 4V to 16V power rails Internal LDO for optimum gate drive voltage 1.5A gate drive current Programmable output voltages Internal soft start Power rail under voltage lockout Hiccup mode short circuit protection SOIC-14 package
Applications
u Graphics processor power supplies on PCI-Express
platform
u Embedded, low cost, high efficiency converters u Point of load power supplies
Typical Application Circuit
12V IN
+
3.3V IN
1
2.5V OUT
PN LDOG LDFB OCS FB COMP NC
DH NC B ST DRV DL GND V CC
14 13 12 11 10 9 8 + 1 2
2 3 4 5 + 6 7
1.5V OUT
SC2621
December 17, 2004
1
www.semtech.com
SC2621
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter Input Supply Voltage BST to GND BST to PN PN to GND PN to GND Negative Pulse (tpulse < 20ns) DL to GND DL to GND Negative Pulse (tpulse < 20ns) DH to PN DH to PN Negative Pulse (tpulse < 20ns) DRV to GND Operating Ambient Temperature Range Operating Junction Temperature Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Lead Temperature (Soldering) 10s Storage Temperature
Symbol VCC VBST VBST_PN VPN VPN_PULSE VDL VDL_PULSE VDH_PN VDH_PULSE VDRV TA TJ JA JC TLEAD TSTG
Maximum 18 40 10 -1 to 30 -5 -1 to +10 -3 -1 to +10 -3 10 -25 to 85 -25 to 125 100 32 300 -65 to 150
Units V V V V V V V V V V C C C/W C/W C C
Electrical Characteristics
Unless specified: VCC = 5V to 16V; VFB = VO; VBST - VPN = 5V to 8.2V; TA = -25 to 85C
Parameter General VCC Supply Voltage VCC Quiescent Current VCC Under Voltage Lockout BST to PN Supply Voltage BST Quiescent Current Internal LDO LDO Output Dropout Voltage
Symbol
Conditions
Min
Typ
Max
Units
VCC IQVCC UVVCC VBST_PN IQBST VCC = 12V, VBST -VPN = 8.2V VCC = 12V, VBST -VPN = 8.2V VHYST = 100mV
4 5 4 4
16 7
V mA V
10 3
V mA
VDRV VDROP
8.6V < VCC < 16V 4V < VCC < 8.6V
8.2 0.4
V V
2003 Semtech Corp.
2
www.semtech.com
SC2621
POWER MANAGEMENT Electrical Characteristics
Unless specified: VCC = 5V to 16V; VFB = VO; VBST - VPN = 5V to 8.2V; TA = -25 to 85C
Parameter Linear Section Reference Voltage Gain
(2)
Symbol
Conditions
Min
Typ
Max
Units
VOL AOLL
LDFB = VOL, TA = 25C, VCC = 12V LDFB to LDOG IO = 0 to 1A , VIN = 3.3V, VCC = 12V VIN = 3.2V to 3.4V, VCC = 12V VIN = 3.3V, VCC = 10V to 14V VGATE = 6.5V VGATE = 6.5V LDFB = 0.5V
0.495
0.500 70
0.505
V dB
Load Regulation Line Regulation VCC Supply Rejection Gate Sourcing Current Gate Sinking Current LDFB Input Bias Current Sw itching Section Reference Voltage Load Regulation Line Regulation Operating Frequency Ramp Amplitude
(2) (2)
0.4 0.4 0.4 1 1 -0.2 -1.0
% % % mA mA uA
VREF
TA = 25C, VCC = 12V IO = 0.2 to 4A VCC = 10V to 14V
0.495
0.500 0.4 0.4
0.505
V % %
FS Vm DMAX tSRC_DH tSINK_DH tSRC_DL tSINK_DL 6V Swing at CL = 3.3nF VBST-VPN = 8.2V 6V Swing at CL = 3.3nF VDRV = 8.2V
400
500 0.8 97 41 27 29 42 30 2 40 80 10 0.9 0.9
600
kHz V % ns ns ns mV nA dB MHz mA mA V/us
Maximum Duty Cycle
DH Rising/Falling Time DL Rising/Falling Time DH, DL Nonoverlapping Time Voltage Error Amplifier Input Offset Voltage Open Loop Gain
(2) (2)
Input Offset Current (2) Unity Gain Bandwidth (2) Output Source Current Output Sink Current Slew Rate
(2)
For CL=500pF Load
1.2
Notes:
(1) This device is ESD sensitive. Use of standard ESD handling precautions is required. (2) Guaranteed by design, not tested in production.
2003 Semtech Corp.
3
www.semtech.com
SC2621
POWER MANAGEMENT Pin Configuration
TOP VIEW
PN LDOG LDFB OCS FB COMP NC 1 2 3 4 5 6 7 14 13 12 11 10 9 8 DH NC BST DRV DL GND VCC
Ordering Information
Part Numbers SC2621STRT(1)(2) P ackag e SO-14
Note: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2). Lead free product. This product is fully WEEE and RoHS compliant.
(SO-14)
Pin Descriptions
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin Name PN LDOG LD F B OCS FB COMP NC VC C GND DL DRV BST NC DH Pin Function Phase node. Connect this pin to bottom N-MOSFET drain. External LDO gate drive. Connect this pin to the external N-MOSFET gate. External LDO feed back. Connect this pin to the linear regulator output. Current limit setting. Connect resistors from this pin to DRV pin and to ground to program the trip point of load current. Refer to Applications Information Section for details. Voltage feed back of sychronous buck converter. Error amplifier output for compensation. No connection. Chip input power supply. Chip ground. Gate drive for bottom MOSFET. Internal LDO output. Connect a 1uF ceramic capasitor from this pin to ground for decoupling. This voltage is used for chip bias, including gate drivers. Boost input for top gate drive bias. No connection. Gate drive for top MOSFET.
2003 Semtech Corp.
4
www.semtech.com
SC2621
POWER MANAGEMENT Block Diagram
8.2V
2003 Semtech Corp.
5
www.semtech.com
SC2621
POWER MANAGEMENT Applications Information
THEORY OPERATION THEOR Y OF OPERATION
The SC2621 integrates a high-speed, voltage mode PWM controller with a linear controller into a single package. It is designed to control two independent output voltages for high performance graphic card applications. As shown in the block diagram of the SC2621, the voltage-mode PWM controller consists of an error amplifier, a 500kHz ramp generator, a PWM comparator, a RS latch circuit, and two MOSFET drivers. The buck converter output voltage is fed back to the error amplifier negative input and is regulated to a reference voltage level. The error amplifier output is compared with the ramp to generate a PWM wave, which is amplified and used to drive the MOSFETs in the buck converter. The PWM wave at the phase node with the amplitude of Vin is filtered out to get a DC output. The linear controller is an error amplifier. It provides the gate drive and output voltage control for a linear regulator. Both PWM controller and linear controller work with soft-start and fault monitoring circuitry to meet application requirement. UVLO, Start Up and Shut Down To initiate the SC2621, a supply voltage is applied to Vcc pin. The top gate (DH) and bottom gate (DL) are held low until Vcc voltage exceed UVLO (Under Voltage Lock Out) threshold, typically 4.0V. Then the internal Soft-Start (SS) capacitor begins to charge, the top gate remains low, and the bottom gate is pulled high to turn on the bottom MOSFET. When the SS voltage at the capacitor reaches 0.4V, the linear controller is enabled and LDO output is turned on. Meanwhile, the top and bottom gates of PWM controller begin to switch. The switching regulator output is slowly ramping up for a soft turn-on. If the supply voltages at Vcc pin falls below UVLO threshold during a normal operation, the SS capacitor begins to discharge. When the SS voltage reaches 0.4V, the PWM controller controls the switching regulator output to ramp down slowly for a soft turn-off. Meanwhile, the linear controller is disabled and LDO output is turned off. Hiccup Mode Short Circuit Protection The SC2621 uses low-side MOSFET Rdson sensing for over current protection. In every switching cycle, after the bottom MOSFET is on for 150ns, the SC2621 detects the phase node voltage and compares it with an internal setting voltage. If the phase node is lower than the setting voltage, an overcurrent condition occurs. The SC2621 will discharge the internal SS capacitor and shut 2003 Semtech Corp. 6
down both outputs. After waiting for around 10 milliseconds, the SC2621 begins to charge SS capacitor again and initiates a fresh startup. The startup and shutdown cycle will repeat until the short circuit is removed. This is called a hiccup mode short circuit protection. To program a load trip point for short circuit protection, it is recommended to connect a 3.3k resistor from the OCS pin to the ground, and a resistor Rset from the OCS pin to the DRV pin, as shown in Fig. 1.
12V 8 11 V CC DRV
Rset 4 OCS
3.3k
SC262 1
GND 9
Fig. 1. Programming load trip point
The resistor Rset can be found in Fig. 2 for a given phase node voltage Vpn at the load trip point. This voltage is the product of the inductor peak current at the load trip point and the Rdson of the low-side MOSFET:
V pn = I peak Rds _ on
The soft start time of the SC2621 is fixed at around 5ms. Therefore, the maximum soft start current is determined by the output inductance and output capacitance. The values of output inductor and output bulk capacitors have to be properly selected so that the soft start peak current does not exceed the load trip point of the short circuit protection. Internal LDO for Gate Drive An internal LDO is designed in the SC2621 to lower the 12V supply voltage for gate drive. An 1uF external ceramic capacitor connected in between DRV pin to the ground is needed to support the LDO. The LDO output is connected to low gate drive internally, and has to beconnected to high gate drive through an external bootstrap circuit. The LDO output voltage is set at 8.2V.
www.semtech.com
SC2621
POWER MANAGEMENT Applications Information (Cont.)
350 325 300 Vpn (mV) 275 250 225 200 175 150 0 100 200 300 Rset (k -ohm) 400 500 600
PS = I O x VIN x t S x f OSC
There is no significant switching loss for the bottom MOSFET because of its zero voltage switching. The conduction losses of the top and bottom MOSFETs are given by:
2 PC _ TOP = I O x Rdson x D 2 PC _ BOT = I O x Rdson x (1 - D )
Fig. 2. Pull down resistor for current limit setting
The manufacture data and bench tested results show that, for low Rdson MOSFETs run at applied load current, the optimum gate drive voltage is around 8.2V, where the total power losses of power MOSFETs are minimized.
If the requirement of total power losses for each MOSFET is given, the above equations can be used to calculate the values of Rdson and gate charge can be calculated using above equations, then the devices can be determined accordingly. The solution should ensure the MOSFET is within its maximum junction temperature at highest ambient temperature. Output Capacitor The output capacitors should be selected to meet both output ripple and transient response criteria. The output capacitor ESR causes output ripple VRIPPLE during the inductor ripple current flowing in. To meet output ripple criteria, the ESR value should be:
COMPONENT SELECTION
General design guideline of switching power supplies can be applied to the component selection for the SC2621. Inductor MOSFETs Induct or and MOSFETs The selection of inductor and MOSFETs should meet thermal requirement because they are power loss dominant components. Pick an inductor with as high inductance as possible without adding extra cost and size. The higher inductance, the lower ripple current, the smaller core loss and the higher efficiency will be. However, too high inductance slows down output transient response. It is recommended to choose the inductance that gives the inductor ripple current to be approximate 20% of maximum load current. So choose inductor value from:
RESR <
L x f OSC x VRIPPLE V VO x (1 - O ) VIN
The output capacitor ESR also causes output voltage transient VT during a transient load current IT flowing in. To meet output transient criteria, the ESR value should be:
RESR <
VT IT
To meet both criteria, the smaller one of above two ESRs is required. The output capacitor value also contributes to load transient response. Based on a worst case where the inductor energy 100% dumps to the output capacitor during the load transient, the capacitance then can be calculated by:
L=
V 5 x VO x (1 - O ) I O x f osc VIN
The MOSFETs are selected from their Rdson, gate charge, and package. The SC2621 provides 1.5A gate drive current. To drive a 50nC gate charge MOSFET gives 50nC/ 1.5A=33ns switching time. The switching time ts contributes to the top MOSFET switching loss:
2003 Semtech Corp. 7
C > Lx
2 IT VT2
www.semtech.com
SC2621
POWER MANAGEMENT Applications Information (Cont.)
Input Capacitor The input capacitor should be chosen to handle the RMS ripple current of a synchronous buck converter. This value is given by:
2 I RMS = (1 - D ) x I IN + D x ( I o - I IN )2
signal model of the buck converter operating at fixed switching frequency. The transfer function of the model is given by:
VO VIN 1 + sRESRC = x VC Vm 1 + sL / R + s 2 LC
where VIN is the power rail voltage, Vm is the amplitude of the 500kHz ramp, and R is the equivalent load.
where Io is the load current, IIN is the input average current, and D is the duty cycle. Choosing low ESR input capacitors will help maximize ripple rating for a given size. MOSFET for Linear Regulator The MOSFET in linear regulator operates in linear region with really high power loss. A device with a suitable package has to be selected to handle the loss. To prevent too high load current during short circuit, the Rdson of the MOSFET should not be selected too low. A good choice is to select a MOSFET so that it is almost fully turned on at maximum load current. For example, in a LDO design with 3.3V in and 1.5V/2A out, a MOSFET with 600 to 800mohm Rdson can be chosen. Bootstrap Circuit The SC2621 uses an external bootstrap circuit to provide a voltage at BST pin for the top MOSFET drive. This voltage, referring to the Phase Node, is held up by a bootstrap capacitor. Typically, it is recommended to use a 1uF ceramic capacitor with 16V rating and a commonly available diode IN4148 for the bootstrap circuit. Filters for Supply Power For each pin of DRV and Vcc, it is recommended to use a 1uF/16V ceramic capacitor for decoupling. In addition, place a small resistor (10 ohm) in between Vcc pin and the supply power for noise reduction.
SC2621 AND MOSFETS
REF FB
+ EA -
Vc
PWM MODULAT OR L OUT Vo
COMP Zf Co
Zs
Resr
Fig. 3. Block diagram of the control loop
The model is a second order system with a finite DC gain, a complex pole pair at Fo, and an ESR zero at Fz, as shown in Fig. 4. The locations of the poles and zero are determined by:
FO =
FZ =
1 LC
1 RESR C
CONTROL LOOP DESIGN
The goal of compensation is to shape the frequency response charateristics of the buck converter to achieve a better DC accuracy and a faster transient response for the output voltage, while maintaining the loop stability. The block diagram in Fig. 3 represents the control loop of a buck converter designed with the SC2621. The control loop consists of a compensator, a PWM modulator, and a LC filter. The LC filter and PWM modulator represent the small
2003 Semtech Corp. 8
The compensator in Fig. 3 includes an error amplifier and impedance networks Zf and Zs. It is implemented by the circuit in Fig. 5. The compensator provides an integrator, double poles and double zeros. As shown in Fig. 4, the integrator is used to boost the gain at low frequency. Two zeros are introduced to compensate excessive phase lag at the loop gain crossover due to the integrator (-90deg) and complex pole pair (-180deg). Two high frequency poles are designed to compensate the ESR zero
www.semtech.com
SC2621
POWER MANAGEMENT Applications Information (Cont.)
and attenuate high frequency noise.
60
Fp1
COM PENSATOR GAI N
(1). Plot the converter gain, including LC filter and PWM modulator. (2). Select the open loop crossover frequency Fc located at 10% to 20% of the switching frequency. At Fc, find the required DC gain. (3). Use the first compensator pole Fp1 to cancel the ESR zero Fz.
Fc
Fp2
30
Fz1 Fz2 Fo
CO NV ER TE RG AI N LO
GAIN (dB)
OP GA IN
0
Fz
-30
(4). Have the second compensator pole Fp2 at half the switching frequency to attenuate the switching ripple and high frequency noise. (5). Place the first compensator zero Fz1 at or below 50% of the power stage resonant frequency Fo.
-60 100 1K 10K FR EQ UENCY (Hz ) 100 K 1M
(6). Place the second compensator zero Fz2 at or below the power stage resonant frequency Fo. A MathCAD program is available upon request for the calculation of the compensation parameters.
Fig. 4. Bode plots for control loop design
C2
LAY LAYOUT GUIDELINES
R2 C3 R3 Vo
2 3
C1 Vc
1
Rtop Rbot
VREF
0.5V
The switching regulator is a high di/dt power circuit. Its Printed Circuit Board (PCB) layout is critical. A good layout can achieve an optimum circuit performance while minimizing the component stress, resulting in better system reliability. During PCB layout, the SC2621 controller, MOSFETs, inductor, and power decoupling capacitors have to be considered as a unit. The following guidelines are typically recommended for using the SC2621 controller.
Fig. 5. Compensation network
The top resistor Rtop of the voltage divider in Fig. 5 can be chosen from 1k to 5k. Then the bottom resistor Rbot is found from:
Rbot =
0.5V x Rtop VO - 0.5V
where 0.5V is the internal reference voltage of the SC2621. The other components of the compensator can be calculated using following design procedure:
2003 Semtech Corp. 9
+
(1). Place a 4.7uF to 10uF ceramic capacitor close to the drain of top MOSFET for the high frequency and high current decoupling. The loop formed by the capacitor, the top and bottom MOSFETs must be as small as possible. Keep the input bulk capacitors close to the drain of the top MOSFETs. (2). Place the SC2621 over a quiet ground plane to avoid pulsing current noise. Keep the ground return of the gate drive short. (3). Connect bypass capacitors as close as possible to the decoupling pins (DRV and Vcc) to the ground pin GND. The trace length of the decoupling capasitor on DRV pin should be no more than 0.2" (5mm). (4). Locate the components of the bootstrap circuit close to the SC2621.
www.semtech.com
SC2621
POWER MANAGEMENT Outline Drawing - SO-14
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.053 .069 .004 .010 .049 .065 .020 .012 .007 .010 .337 .341 .344 .150 .154 .157 .236 BSC .050 BSC .010 .020 .016 .028 .041 (.041) 14 0 8 .004 .010 .008 1.75 1.35 0.10 0.25 1.25 1.65 0.31 0.51 0.17 0.25 8.55 8.65 8.75 3.80 3.90 4.00 6.00 BSC 1.27 BSC 0.25 0.50 0.40 0.72 1.04 (1.04) 14 0 8 0.10 0.25 0.20
A N
2X
e
D
DIM
A A1 A2 b c D E1 E e h L L1 N 01 aaa bbb ccc
E/2 E1 E
ccc C 1 2X N/2 TIPS
2
3 B
D aaa C A2 A SEATING PLANE C A1 C A-B D
h h
bxN bbb
H GAGE PLANE 0.25
c
SIDE VIEW
NOTES: 1. 2. 3. 4.
SEE DETAIL
A
L (L1) DETAIL
01
A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -HDIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. REFERENCE JEDEC STD MS-012, VARIATION AB.
Land Pattern - SO-14
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.205) .118 .050 .024 .087 .291 (5.20) 3.00 1.27 0.60 2.20 7.40
Y P
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. REFERENCE IPC-SM-782A, RLP NO. 302A.
2.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
2003 Semtech Corp. 10 www.semtech.com

▲Up To Search▲

Price & Availability of SC2621STRT

	To Download SC2621STRT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .